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rev 1.1.8 3/31/04 characteristics subject to change without notice. 1 of 22 www.xicor.com low noise/low power/spi bus x9400 quad digitally controlled potentiometers (xdcp ) features four potentiometers per package 64 resistor taps spi serial interface for write, read, and transfer operations of the potentiometer wiper resistance, 40 ? typical at 5v. four non-volatile data registers for each potentiometer non-volatile storage of multiple wiper position ? o wer on recall. loads saved wiper position on power up. standby current < 1? max system v cc : 2.7v to 5.5v operation analog v + /v : -5v to +5v 10k ? , 2.5k ? end to end resistance 100 yr. data retention endurance: 100,000 data changes per bit per register ? ow power cmos 24-lead soic, 24-lead tssop, and 24-lead csp (chip scale package) packages description the x9400 integrates four digitally controlled potentiometers (xdcps) on a monolithic cmos integrated circuit. the digitally controlled potentiometer is implemented using 63 resistive elements in a series array. between each element are tap points connected to the wiper terminal through switches. the position of the wiper on the array is controlled by the user through the spi serial bus interface. each potentiometer has associated with it a volatile wiper counter register (wcr) and four nonvolatile data registers (dr0-3) that can be directly written to and read by the user. the contents of the wcr controls the position of the wiper on the resistor array through the switches. po w er up recalls the contents of dr0 to the wcr. the xdcp can be used as a three-terminal potentiometer or as a two-terminal variable resistor in a wide variety of applications including control, parameter adjustments, and signal processing. block diagram interface and control circuitry cs sck so a0 a1 r0 r1 r2 r3 wiper counter register (wcr) resistor array pot 1 v h1 /r h1 v l1 /r l1 r0 r1 r2 r3 wiper counter register (wcr) v h0 /r h0 v l0 /r l0 data 8 v w0 /r w0 v w1 /r w1 r0 r1 r2 r3 resistor array v h2 /r h2 v l2 /r l2 v w2 /r w2 r0 r1 r2 r3 resistor array v h3 /r h3 v l3 /r l3 v w3 /r w3 wiper counter register (wcr) wiper counter register (wcr) pot 3 pot 2 hold pot 0 v cc v ss wp si v+ v- a pplication n otes available an99 ?an115 ?an120 ?an124 ?an133 ?an134 ?an135
x9400 characteristics subject to change without notice. 2 of 22 rev 1.1.8 3/31/04 www.xicor.com pin descriptions host interface pins serial output (so) so is a push/pull serial data output pin. during a read cycle, data is shifted out on this pin. data is clocked out by the falling edge of the serial clock. serial input si is the serial data input pin. all opcodes, byte addresses and data to be written to the pots and pot registers are input on this pin. data is latched by the r ising edge of the serial clock. serial clock (sck) the sck input is used to clock data into and out of the x9400. chip select (cs ) when cs is high, the x9400 is deselected and the so pin is at high impedance, and (unless an internal write cycle is underway) the device will be in the standby state. cs low enables the x9400, placing it in the active power mode. it should be noted that after a power-up, a high to low transition on cs is required prior to the start of any operation. hold (hold ) hold is used in conjunction with the cs pin to select the device. once the part is selected and a serial sequence is underway, hold may be used to pause the serial communication with the controller without resetting the serial sequence. to pause, hold m ust be brought low while sck is low. to resume communication, hold is brought high, again while sck is low. if the pause feature is not used, hold should be held high at all times. device address (a 0 a 1 ) the address inputs are used to set the least signi?ant 2 bits of the 8-bit slave address. a match in the slave address serial data stream must be made with the address input in order to initiate communication with the x9400. a maximum of 4 devices may occupy the spi serial bus. potentiometer pins v h /r h (v h0 /r h0 ? h3 /r h3 ), v l /r l (v l0 /r l0 ? l3 /r l3 ) the v h /r h and v l /r l inputs are equivalent to the terminal connections on either end of a mechanical potentiometer. v w /r w (v w0 /r w0 ? w3 /r w3 ) the wiper outputs are equivalent to the wiper output of a mechanical potentiometer. hardware write protect input (wp ) the wp pin when low prevents nonvolatile writes to the data registers. analog supplies (v+, v-) the analog supplies v+, v- are the supply voltages for the xdcp analog section. pin configuration v cc v l0 /r l0 v h0 /r h0 wp si a 1 1 2 3 4 5 6 7 8 9 10 24 23 22 21 20 19 18 17 16 15 v+ v l3 /r l3 v h3 /r h3 v w3 /r w3 a 0 so hold sck v l2 /r l2 v h2 /r h2 soic x9400 v ss v w0 /r w0 14 13 11 12 cs v l1 /r l1 v h1 /r h1 v w1 /r w1 v w2 /r w2 v- si a 1 v h2 /r h2 1 2 3 4 5 6 7 8 9 10 24 23 22 21 20 19 18 17 16 15 wp cs v w0 /r w0 v cc v+ v l3 /r l3 v h3 /r h3 v w3 /r w3 tssop x9400 v w2 /r w2 14 13 11 12 hold v l1 /r l1 v h1 /r h1 v w1 /r w1 a 0 so v h0 /r h0 v- sck v l2 /r l2 v l0 /r l0 v ss 2 3 4 a b c d e f top view?umps down v w0 /r w0 v l0 /r l0 v+ a 0 hold v l1 /r l1 v cc v l3 /r l3 v w3 /r w3 so si v w1 /r w1 sck v l2 /r l2 wp v- v h0 /r h0 v h1 /r h1 v h3 /r h3 v h2 /r h2 v ss v w2 /r w2 cs a 1 1 csp
x9400 characteristics subject to change without notice. 3 of 22 rev 1.1.8 3/31/04 www.xicor.com pin names device description the x9400 is a highly integrated microcircuit incorporating four resistor arrays and their associated registers and counters and the serial interface logic providing direct communication between the host and the xdcp potentiometers. serial interface the x9400 supports the spi interface hardware conventions. the device is accessed via the si input with data clocked in on the rising sck. cs m ust be low and the hold and wp pins must be high during the entire operation. the so and si pins can be connected together, since they have three state outputs. this can help to reduce system pin count. array description the x9400 is comprised of four resistor arrays. each array contains 63 discrete resistive segments that are connected in series. the physical ends of each array are equivalent to the ?ed terminals of a mechanical potentiometer (v h /r h and v l /r l inputs). at both ends of each array and between each resistor segment is a cmos switch connected to the wiper (v w /r w ) output. within each individual array only one s witch may be turned on at a time. these switches are controlled by a wiper counter register (wcr). the six bits of the wcr are decoded to select, and enable, one of sixty-four switches. wiper counter register (wcr) the x9400 contains four wiper counter registers, one for each xdcp potentiometer. the wcr is equivalent to a serial-in, parallel-out register/counter with its outputs decoded to select one of sixty-four s witches along its resistor array. the contents of the wcr can be altered in four ways: it may be written directly by the host via the write wiper counter register instruction (serial load); it may be written indirectly by transferring the contents of one of four associated data registers via the xfr data register or global xfr data register instructions (parallel load); it can be modi?d one step at a time by the increment/ decrement instruction. finally, it is loaded with the contents of its data register zero (dr0) upon power- up. the wiper counter register is a volatile register; that is, its contents are lost when the x9400 is powered- down. although the register is automatically loaded with the value in dr0 upon power-up, this may be different from the value present at power-down. data registers each potentiometer has four 6-bit nonvolatile data registers. these can be read or written directly by the host. data can also be transferred between any of the f our data registers and the associated wiper counter register. all operations changing data in one of the data registers is a nonvolatile operation and will take a maximum of 10ms. if the application does not require storage of multiple settings for the potentiometer, the data registers can be used as regular memory locations for system parameters or user preference data. data register detail symbol description sck serial clock si, so serial data a 0 -a 1 device address v h0 /r h0 ? h3 /r h3 , v l0 /r l0 ? l3 /r l3 potentiometer pins (terminal equivalent) v w0 /r w0 ? w1 /r w1 potentiometer pins (wiper equivalent) wp hardware write protection v cc system supply voltage v ss system ground nc no connection (msb) (lsb) d5 d4 d3 d2 d1 d0 nv nv nv nv nv nv
x9400 characteristics subject to change without notice. 4 of 22 rev 1.1.8 3/31/04 www.xicor.com write in process the contents of the data registers are saved to nonvolatile memory when the cs pin goes from low to high after a complete write sequence is received by the device. the progress of this internal write operation can be monitored by a write in process bit (wip). the wip bit is read with a read status command. instructions identification (id) byte the ?st byte sent to the x9400 from the host, following a cs going high to low, is called the identi?ation b yte. the most signi?ant four bits of the slave address are a device type identi?r, for the x9400 this is ?ed as 0101[b] (refer to figure 2). the two least signi?ant bits in the id byte select one of f our devices on the bus. the physical device address is de?ed by the state of the a 0 -a 1 input pins. the x9400 compares the serial data stream with the address input state; a successful compare of both address bits is required for the x9400 to successfully continue the command sequence. the a 0 ? 1 inputs can be actively driven by cmos input signals or tied to v cc or v ss . the remaining two bits in the slave byte must be set to 0. figure 2. identification byte format instruction byte the next byte sent to the x9400 contains the instruction and register pointer information. the four most signi?ant bits are the instruction. the next four bits point to one of the four pots and, when applicable, they point to one of four associated registers. the fo r mat is shown below in figure 3. 1 00 00 a1 a0 device type identifier device address 1 figure 1. detailed potentiometer block diagram serial data path from interface circuitry register 0 register 1 register 2 register 3 serial bus input parallel bus input wiper counter register inc/dec logic up/dn clk modified scl up/dn v h /r h v l /r l v w /r w if wcr = 00[h] then v w /r w = v l /r l if wcr = 3f[h] then v w /r w = v h /r h 8 6 c o u n t e r d e c o d e (wcr) (one of four arrays)
x9400 characteristics subject to change without notice. 5 of 22 rev 1.1.8 3/31/04 www.xicor.com figure 3. instruction byte format the four high order bits of the instruction byte specify the operation. the next two bits (r 1 and r 0 ) select one of the four registers that is to be acted upon when a register oriented instruction is issued. the last two bits (p1 and p 0 ) selects which one of the four potentiometers is to be affected by the instruction. f our of the ten instructions are two bytes in length and end with the transmission of the instruction byte. these instructions are: xfr data register to wiper counter register ?his transfers the contents of one speci?d data register to the associated wiper counter register. xfr wiper counter register to data register ?his transfers the contents of the speci?d wiper counter register to the speci?d associated data register. global xfr data register to wiper counter register this transfers the contents of all speci?d data registers to the associated wiper counter registers. global xfr wiper counter register to data register this transfers the contents of all wiper counter registers to the speci?d associated data registers. the basic sequence of the two byte instructions is illustrated in figure 4. these two-byte instructions e xchange data between the wcr and one of the data registers. a transfer from a data register to a wcr is essentially a write to a static ram, with the static ram controlling the wiper position. the response of the wiper to this action will be delayed by t wrl . a transfer from the wcr (current wiper position), to a data register is a write to nonvolatile memory and takes a minimum of t wr to complete. the transfer can occur between one of the four potentiometers and one of its associated registers; or it may occur globally, where the transfer occurs between all potentiometers and one associated register. five instructions require a three-byte sequence to complete. these instructions transfer data between the host and the x9400; either between the host and one of the data registers or directly between the host and the wiper counter register. these instructions are: read wiper counter register ?ead the current wiper position of the selected pot, ?r ite wiper counter register ?hange current wiper position of the selected pot, read data register ?ead the contents of the selected data register; ?r ite data register ?rite a new value to the selected data register. read status ?his command returns the contents of the wip bit which indicates if the internal write cycle is in progress. the sequence of these operations is shown in figure 5 and figure 6. the ?al command is increment/decrement. it is different from the other commands, because its length is indeterminate. once the command is issued, the master can clock the selected wiper up and/or down in one resistor segment steps; thereby, providing a ?e tuning capability to the host. for each sck clock pulse (t high ) while si is high, the selected wiper will move one resistor segment towards the v h /r h terminal. similarly, f or each sck clock pulse while si is low, the selected wiper will move one resistor segment towards the v l /r l terminal. a detailed illustration of the sequence and timing for this operation are shown in figure 7 and figure 8. i1 i2 i3 i0 r1 r0 p1 p0 pot select register select instructions
x9400 characteristics subject to change without notice. 6 of 22 rev 1.1.8 3/31/04 www.xicor.com figure 4. two-byte instruction sequence figure 5. three-byte instruction sequence (write) figure 6. three-byte instruction sequence (read) figure 7. increment/decrement instruction sequence 010100a1a0 i3 i2 i1 i0 r1 r0 p1 p0 sck si cs 0 101 a1 a0 i3 i2 i1 i0 r1 r0 p1 p0 sck si 00d5 d4 d3 d2 d1 d0 cs 00 0 101 a1 a0 i3 i2 i1 i0 r1 r0 p1 p0 sck si cs 00 s0 00d5 d4 d3 d2 d1 d0 don? care 010100a1a0 i3 i2 i1 i0 0 p1 p0 sck si i n c 1 i n c 2 i n c n d e c 1 d e c n 0 cs
x9400 characteristics subject to change without notice. 7 of 22 rev 1.1.8 3/31/04 www.xicor.com figure 8. increment/decrement timing limits table 1. instruction set instruction instruction set operation i 3 i 2 i 1 i 0 r 1 r 0 p 1 p 0 read wiper counter register 1 0010 0p 1 p 0 read the contents of the wiper counter register pointed to by p 1 -p 0 write wiper counter register 1 0100 0p 1 p 0 write new value to the wiper counter register pointed to by p 1 -p 0 read data register 1 0 1 1 r 1 r 0 p 1 p 0 read the contents of the data register pointed to by p 1 -p 0 and r 1 ? 0 write data register 1 1 0 0 r 1 r 0 p 1 p 0 write new value to the data register pointed to by p 1 -p 0 and r 1 ? 0 xfr data register to wiper counter register 1 101r 1 r 0 p 1 p 0 transfer the contents of the data register pointed to by r 1 ? 0 to the wiper counter register pointed to by p 1 -p 0 xfr wiper counter register to data register 1 110r 1 r 0 p 1 p 0 transfer the contents of the wiper counter register pointed to by p 1 -p 0 to the register pointed to by r 1 ? 0 global xfr data register to wiper counter register 0 001r 1 r 0 00 transfer the contents of the data registers pointed to by r 1 ? 0 of all four pots to their respective wiper counter register global xfr wiper counter register to data register 1 000r 1 r 0 00 transfer the contents of all wiper counter registers to their respective data registers pointed to by r 1 ? 0 of all four pots increment/decrement wiper counter register 0 0100 0p 1 p 0 enable increment/decrement of the wiper counter register pointed to by p 1 -p 0 read status (wip bit) 0 1010 0 0 1 read the status of the internal write cycle, by checking the wip bit. sck si v w /r w inc/dec cmd issued t wrid voltage out
x9400 characteristics subject to change without notice. 8 of 22 rev 1.1.8 3/31/04 www.xicor.com instruction format notes: (1) ?1 ~ a0? stands for the device addresses sent by the master. (2) wpx refers to wiper position data in the counter register (3) ?? stands for the increment operation, si held high during active sck phase (high). (4) ?? stands for the decrement operation, si held low during active sck phase (high). read wiper counter register (wcr) write wiper counter register (wcr) read data register (dr) write data register (dr) transfer data register (dr) to wiper counter register (wcr) transfer wiper counter register (wcr) to data register (dr) cs falling edge device type identifier device addresses instruction opcode wcr addresses wiper position (sent by x9400 on so) cs rising edge 010100 a 1 a 0 100100 p 1 p 0 00 w p 5 w p 4 w p 3 w p 2 w p 1 w p 0 cs falling edge device type identifier device addresses instruction opcode wcr addresses data byte (sent by host on si) cs rising edge 010100 a 1 a 0 101000 p 1 p 0 00 w p 5 w p 4 w p 3 w p 2 w p 1 w p 0 cs falling edge device type identifier device addresses instruction opcode dr and wcr addresses data byte (sent by x9400 on so) cs rising edge 010100 a 1 a 0 1011 r 1 r 0 p 1 p 0 00 w p 5 w p 4 w p 3 w p 2 w p 1 w p 0 cs falling edge device type identifier device addresses instruction opcode dr and wcr addresses data byte (sent by host on si) cs rising edge high-voltage write cycle 010100 a 1 a 0 1100 r 1 r 0 p 1 p 0 00 w p 5 w p 4 w p 3 w p 2 w p 1 w p 0 cs falling edge device type identifier device addresses instruction opcode dr and wcr addresses cs rising edge 010100 a 1 a 0 1101 r 1 r 0 p 1 p 0 cs falling edge device type identifier device addresses instruction opcode dr and wcr addresses cs rising edge high-voltage write cycle 010100 a 1 a 0 1110 r 1 r 0 p 1 p 0
x9400 characteristics subject to change without notice. 9 of 22 rev 1.1.8 3/31/04 www.xicor.com increment/decrement wiper counter register (wcr) global transfer data register (dr) to wiper counter register (wcr) global transfer wiper counter register (wcr) to data register (dr) read status cs falling edge device type identifier device addresses instruction opcode wcr addresses increment/decrement (sent by master on sda) cs rising edge 010100 a 1 a 0 0010xx p 1 p 0 i/ d i/ d .... i/ d i/ d cs falling edge device type identifier device addresses instruction opcode dr addresses cs rising edge 010100 a 1 a 0 0001 r 1 r 0 00 cs falling edge device type identifier device addresses instruction opcode dr addresses cs rising edge high-voltage write cycle 010100 a 1 a 0 1000 r 1 r 0 00 cs falling edge device type identifier device addresses instruction opcode wiper addresses data byte (sent by x9400 on so) cs rising edge 010100 a 1 a 0 010100010000000 w i p
x9400 characteristics subject to change without notice. 10 of 22 rev 1.1.8 3/31/04 www.xicor.com absolute maximum ratings t emperature under bias.................... ?5 c to +135 c storage temperature......................... ?5 c to +150 c v oltage on sck, scl or any address input with respect to v ss ........................ ?v to +7v v oltage on v+ (referenced to v ss ) .........................10v v oltage on v- (referenced to v ss ) ........................ -10v (v+) ?(v-) ..............................................................12v any v h .....................................................................v+ any v l ......................................................................v- lead temperature (soldering, 10 seconds) ........ 300 c i w (10 seconds) ................................................?2ma comment stresses above those listed under ?bsolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device (at these or any other conditions above those listed in the operational sections of this speci?ation) is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. recommended operating conditions temperature min. max. commercial 0 c +70 c industrial ?0 c +85 c device supply voltage (v cc ) limits x9400 5v 10% x9400-2.7 2.7v to 5.5v analog characteristics (over recommended operating conditions unless otherwise stated.) notes: (1) absolute linearity is utilized to determine actual wiper voltage versus expected voltage as determined by wiper position whe n used as a potentiometer. (2) relative linearity is utilized to determine the actual change in voltage between two successive tap positions when used as a potentiometer. it is a measure of the error in step size. (3) mi = rtot/63 or (r h ? l )/63, single pot symbol parameter limits test conditions min. typ. max. unit r total end to end resistance ?0 % power rating 50 mw 25 c, each pot i w wiper current ? ma r w wiper resistance 150 250 ? wiper current = 1ma, v cc = 3v 40 100 ? wiper current = 1ma, v cc = 5v vv+ voltage on v+ pin x9400 +4.5 +5.5 v x9400-2.7 +2.7 +5.5 vv- voltage on v- pin x9400 -5.5 -4.5 v x9400-2.7 -5.5 -2.7 v term voltage on any v h /r h or v l /r l pin v- v+ v noise -120 dbv ref: 1khz resolution 1.6 % absolute linearity (1) -1 +1 mi (3) r w(n)(actual) ? w(n)(expected) relative linearity (2) -0.2 +0.2 mi (3) r w(n + 1) ?r w(n) + mi ] temperature coefficient of r total 300 ppm/ c ratiometric temp. coefficient ?0 ppm/? c h /c l /c w potentiometer capacitances 10/10/25 pf see spice macromodel i al r h , r l , r w leakage current 0.1 10 ? v in = v ss to v cc . device is in stand-by mode.
x9400 characteristics subject to change without notice. 11 of 22 rev 1.1.8 3/31/04 www.xicor.com d.c. operating characteristics (over the recommended operating conditions unless otherwise specified.) endurance and data retention capacitance power-up timing symbol parameter limits test conditions min. typ. max. units i cc1 v cc supply current (active) 400 ? f sck = 2mhz, so = open, other inputs = v ss i cc2 v cc supply current (nonvol- atile write) 1maf sck = 2mhz, so = open, other inputs = v ss i sb v cc current (standby) 1 a sck = si = v ss , addr. = v ss i li input leakage current 10 ? v in = v ss to v cc i lo output leakage current 10 ? v out = v ss to v cc v ih input high voltage v cc x 0.7 v cc + 0.5 v v il input low voltage ?.5 v cc x 0.1 v v ol output low voltage 0.4 v i ol = 3ma parameter min. unit minimum endurance 100,000 data changes per bit per register data retention 100 years symbol test max. unit test conditions c out (4) output capacitance (so) 8 pf v out = 0v c in (4) input capacitance (a0, a1, si, and sck) 6 pf v in = 0v symbol parameter min. max. unit t pur (5) power-up to initiation of read operation 1 ms t puw (5) power-up to initiation of write operation 5 ms t r v cc (4) v cc power up ramp 0.2 50 v/msec power up requirements (power up sequencing can affect correct recall of the wiper registers) the preferred power-on sequence is as follows: first v cc , then the potentiometer pins, r h , r l , and r w . v oltage should not be applied to the potentiometer pins before v+ or v- is applied. the v cc r amp rate speci? cation should be met, and any glitches or slope changes in the v cc line should be held to <100mv if possible. if v cc powers down, it should be held below 0.1v for more than 1 second before powering up again in order for proper wiper register recall. also, v cc should not reverse polarity by more than 0.5v. recall of wiper position will not be complete until v cc , v+ and v- reach their ?al value. equivalent a.c. load circuit 5v 1533 ? 100pf sda output
x9400 characteristics subject to change without notice. 12 of 22 rev 1.1.8 3/31/04 www.xicor.com a.c. test conditions notes: (4) this parameter is periodically sampled and not 100% tested (5) t pur and t puw are the delays required from the time the third (last) power supply (v cc , v+ or v-) is stable until the speci? instruction can be issued. these parameters are periodically sampled and not 100% tested. spice macro model symbol table i nput pulse levels v cc x 0.1 to v cc x 0.9 input rise and fall times 10ns input and output timing level v cc x 0.5 10pf r h r total c h 25pf c w c l 10pf r w r l waveform inputs outputs must be steady will be steady may change from low to high will change from low to high may change from high to low will change from high to low don? care: changes allowed changing: state not known n/a center line is high impedance ac timing symbol parameter min. max. unit f sck ssi/spi clock frequency 2.0 mhz t cyc ssi/spi clock cycle time 500 ns t wh ssi/spi clock high time 200 ns t wl ssi/spi clock low time 200 ns t lead lead time 250 ns t lag lag time 250 ns t su si, sck, hold and cs input setup time 50 ns t h si, sck, hold and cs input hold time 50 ns t ri si, sck, hold and cs input rise time 2 s t fi si, sck, hold and cs input fall time 2 s t dis so output disable time 0 500 ns t v so output valid time 100 ns t ho so output hold time 0 ns t ro so output rise time 50 ns t fo so output fall time 50 ns t hold hold time 400 ns t hsu hold setup time 100 ns t hh hold hold time 100 ns t hz hold low to output in high z 100 ns t lz hold high to output in low z 100 ns t i noise suppression time constant at si, sck, hold and cs inputs 20 ns t cs cs deselect time 2 s t wpasu wp , a0 and a1 setup time 0 ns t wpah wp , a0 and a1 hold time 0 ns
x9400 characteristics subject to change without notice. 13 of 22 rev 1.1.8 3/31/04 www.xicor.com high-voltage write cycle timing xdcp timing timing diagrams input timing output timing symbol parameter typ. max. unit t wr high-voltage write cycle time (store instructions) 5 10 ms symbol parameter min. max. unit t wrpo wiper response time after the third (last) power supply is stable 10 ? t wrl wiper response time after instruction issued (all load instructions) 10 ? t wrid wiper response time from an active scl/sck edge (increment/decrement instruction) 450 ns ... cs sck si so msb lsb high impedance t lead t h t su t fi t cs t lag t cyc t wl ... t ri t wh ... cs sck so si addr msb lsb t dis t ho t v ...
x9400 characteristics subject to change without notice. 14 of 22 rev 1.1.8 3/31/04 www.xicor.com hold timing xdcp timing (for all load instructions) xdcp timing (for increment/decrement instruction) ... cs sck so si hold t hsu t hh t lz t hz t hold t ro t fo ... cs sck si msb lsb v w /r w t wrl ... so high impedance ... cs sck so si addr t wrid high impedance v w /r w ... inc/dec inc/dec ...
x9400 characteristics subject to change without notice. 15 of 22 rev 1.1.8 3/31/04 www.xicor.com write protect and device address pins timing cs wp a0 a1 t wpasu t wpah (any instruction)
x9400 characteristics subject to change without notice. 16 of 22 rev 1.1.8 3/31/04 www.xicor.com applications information basic configurations of electronic potentiometers application circuits v r v w /r w +v r i three terminal potentiometer; va r iable voltage divider tw o terminal variable resistor; va r iable current noninverting amplifier voltage regulator offset voltage adjustment comparator with hysteresis + v s v o r 2 r 1 v o = (1+r 2 /r 1 )v s r 1 r 2 i adj v o (reg) = 1.25v (1+r 2 /r 1 )+i adj r 2 v o (reg) v in 317 + v s v o r 2 r 1 v ul = {r 1 /(r 1 +r 2 )} v o (max) v ll = {r 1 /(r 1 +r 2 )} v o (min) 100k ? 10k ? 10k ? 10k ? -12v +12v tl072 + v s v o r 2 r 1 } }
x9400 characteristics subject to change without notice. 17 of 22 rev 1.1.8 3/31/04 www.xicor.com application circuits (continued) inverting amplifier equivalent l-r circuit + v s v o r 2 r 1 z in = r 2 + s r 2 (r 1 + r 3 ) c 1 = r 2 + s leq (r 1 + r 3 ) >> r 2 + v s function generator } } v o = g v s g = - r 2 /r 1 r 2 c 1 r 1 r 3 z in + r 2 + r 1 } } r a r b frequency r 1 , r 2 , c amplitude r a , r b c attenuator filter + v s v o r 3 r 1 v o = g v s -1/2 g +1/2 g o = 1 + r 2 /r 1 fc = 1/(2prc) r 2 r 4 all r s = 10k ? + v s r 2 r 1 r c v o
x9400 characteristics subject to change without notice. 18 of 22 rev 1.1.8 3/31/04 www.xicor.com packaging information 1. all dimensions in inches (in parentheses in millimeters) 2. package dimensions exclude molding flash 0.022 (0.56) 0.014 (0.36) 0.150 (3.81) 0.125 (3.18) 0.625 (15.87) 0.600 (15.24) 0.110 (2.79) 0.090 (2.29) 1.265 (32.13) 1.230 (31.24) 1.100 (27.94) ref. pin 1 index 0.162 (4.11) 0.140 (3.56) 0.030 (0.76) 0.015 (0.38) pin 1 seating plane 0.065 (1.65) 0.040 (1.02) 0.557 (14.15) 0.530 (13.46) 0.080 (2.03) 0.065 (1.65) 0 15 24-lead plastic dual in-line package type p typ. 0.010 (0.25) note:
x9400 characteristics subject to change without notice. 19 of 22 rev 1.1.8 3/31/04 www.xicor.com packaging information 0.290 (7.37) 0.299 (7.60) 0.393 (10.00) 0.420 (10.65) 0.014 (0.35) 0.020 (0.50) pin 1 pin 1 index 0.050 (1.27) 0.598 (15.20) 0.610 (15.49) 0.003 (0.10) 0.012 (0.30) 0.092 (2.35) 0.105 (2.65) (4x) 7 24-lead plastic small outline gull wing package type s note: all dimensions in inches (in parentheses in millimeters) 0.420" 0.050" typical 0.050" typical 0.030" typical 24 places footprint 0.010 (0.25) 0.020 (0.50) 0.015 (0.40) 0.050 (1.27) 0.009 (0.22) 0.013 (0.33) 0??8 x 45
x9400 characteristics subject to change without notice. 20 of 22 rev 1.1.8 3/31/04 www.xicor.com packaging information note: all dimensions in inches (in parentheses in millimeters) 24-lead plastic, tssop package type v .169 (4.3) .177 (4.5) .252 (6.4) bsc .026 (.65) bsc .303 (7.70) .311 (7.90) .002 (.06) .005 (.15) .047 (1.20) .0075 (.19) .0118 (.30) see detail ? .031 (.80) .041 (1.05) .010 (.25) .020 (.50) .030 (.75) gage plane seating plane detail a (20x) (4.16) (7.72) (1.78) (0.42) (0.65) all measurements are typical 08
x9400 characteristics subject to change without notice. 21 of 22 rev 1.1.8 3/31/04 www.xicor.com packaging information package dimensions symbol millimeters min nominal max package width a 2.595 2.625 2.655 package length b 3.814 3.844 3.874 package height c 0.644 0.677 0.710 body thickness d 0.444 0.457 0.470 ball height e 0.280 0.300 0.320 ball diameter f 0.350 0.370 0.390 ball pitch ?width j 0.5 ball pitch ?length k 0.5 ball to edge spacing ?width l 0.538 0.563 0.588 ball to edge spacing ?length m 0.647 0.672 0.697 ball matrix 4321 a rl1 a1 cs rw0 b rw1 si wp rl0 c vss rh1 rh0 vcc d v- rh2 rh3 v+ e rw2 hold so rl3 f rl2 sck a0 rw3 9400wrr yww i2.7 lot # 24-bump chip scale package (csp b24) package outline drawing top view (sample marking) bottom view (bumped side) side view side view a a4 a3 a2 a1 b4 b3 b2 b1 c4 c3 c2 c1 d4 d3 d2 d1 e4 e3 e2 e1 f4 f3 f2 f1 f j m lk b d e e c
x9400 characteristics subject to change without notice. 22 of 22 limited warranty devices sold by xicor, inc. are covered by the warranty and patent indemni?ation provisions appearing in its terms of sale onl y. xicor, inc. makes no warranty, e xpress, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the descr ibed devices from patent infringement. xicor, inc. makes no warranty of merchantability or ?ness for any purpose. xicor, inc. reserves the right to discontinue produ ction and change speci?ations and prices at any time and without notice. xicor, inc. assumes no responsibility for the use of any circuitry other than circuitry embodied in a xicor, inc. product. no o ther circuits, patents, or licenses are implied. trademark disclaimer: xicor and the xicor logo are registered trademarks of xicor, inc. autostore, direct write, block lock, serialflash, mps, and xd cp are also trademarks of xicor, inc. all others belong to their respective owners. u .s. patents xicor products are covered by one or more of the following u.s. patents: 4,326,134; 4,393,481; 4,404,475; 4,450,402; 4,486,769; 4,488,060; 4,520,461; 4,533,846; 4,599,706; 4,617,652; 4,668,932; 4,752,912; 4,829,482; 4,874,967; 4,883,976; 4,980,859; 5,012,132; 5,003,197; 5,023,694; 5,084, 667; 5,153,880; 5,153,691; 5,161,137; 5,219,774; 5,270,927; 5,324,676; 5,434,396; 5,544,103; 5,587,573; 5,835,409; 5,977,585. foreign patents and addition al patents pending. life related policy in situations where semiconductor component failure may endanger life, system designers using this product should design the sy stem with appropriate error detection and correction, redundancy and back-up features to prevent such an occurrence. xicors products are not authorized for use in critical components in life support devices or systems. 1. life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) sup port or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to res ult in a signi?ant injury to the user. 2. a critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. ?icor, inc. 2003 patents pending rev 1.1.8 3/31/04 www.xicor.com ordering information device v cc limits blank = 5v 10% ?.7 = 2.7 to 5.5v t emperature range blank = commercial = 0 c to +70 c i = industrial = ?0 c to +85 c package s24 = 24-lead soic v24 = 24-lead tssop b24 = 24-lead csp (production quantity sold in tape and reel) p otentiometer organization p ot 0 pot 1 pot 2 pot 3 w = 10k ? 10k ? 10k ? 10k ? y = 2.5k ? 2.5k ? 2.5k ? 2.5k ? x9400 p t v y

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